Parasitic Extraction Based Interview Questions

NOTE: I have updated this post recently. Few more questions you will find in another post and I will post the link of that asap.

In this post we are discussing about the Parasitic Extraction related Interview Questions. Remember- I am also listing the Expected Ans in one word or one sentence. But expect the WHY/HOW as part of follow-on question. I have mentioned few follow-on questions also (without Ans). For the detailed ans of any topic, please read the different articles in the ( VLSI CONCEPTS ) http://vlsi-expert.com or refer any other book/weblink.

 

 Parasitic Extraction related

• Q: What are the extraction tools you know/you experienced?
• Expected answer (any): Synopsys(StarRC), Cadence(QRC), Mentor Calibre/xRC, etc.
• Follow On Questions:
• How much comfortable you are in a specific tool?
• What's the difference across the different tools? (if you have know more then 1 tool)
• List down 1 good and 1 bad thing about a specific tool?
• Which one is the industry standard one?
• What is the role of extraction tools in design?
• Q: What are the different inputs of extraction tool?
• Expected answer: Atleast 1 from this "LEF/DEF, mwlib, gds" (or similar type of any physical view), extraction model (like nxtgrd, tluplus), general setup scripts.
• Q: What are the different types/Formats of output of the Extraction Tool or the Parasitic Data?
• Expected Answer:  SPF, DSPF, RSPF, SPEF, SBPF, SPICE, and SSPEFBinary interface.
• Follow on Question:
• What is the difference in all these formats?
• Which one is more accurate?
• Q: What type of information, we can obtain after running the extraction tool?
• Expected answer: Resistance and Capacitance of wires (either lumped or distributed)
• Q: How many different type of capacitance from design point of view?
• Expected answer: capacitance to ground - (Ground cap), capacitance between 2 metal wire of same type (coupling) , Fringe Cap, capacitance between 2 metal wire of different layers
• Follow On Question:
• What do you mean by Ground Cap?
• What do you mean by Fringe cap?
• There are 3 Metals- M1, M2 and M3. How many different types of Cap will be here?
• What do you mean by Area capacitance or Surface Capacitance?
• What do you mean by Total Capacitance?
• Q: What’s the Formula of the Capacitance?
• Expected Answer: C=εA/D=εW.L/D
• Follow On Question:
• Please identify the different parameter in the above Formula for Ground Cap and Coupling cap in terms of Design parameters.
• Expected Ans:
• For Ground Cap : D -> Distance between the two metal plates -> thickness of the dielectric material between the 2 Metals. ; W -> Width of the metal Wire.
• For coupling Cap : D -> Space between the 2 metal plates. W -> Thickness of the Metals.
• For coupling cap and ground cap- is there different dielectric constant or it’s same? If it’s different why?
• What are the different component / parameter with in the design on which Total capacitance has dependency?
• What’s the concept behind the low K dielectric in the parasitic extraction?
• In lower technology, coupling capacitance is always a challenge. For reducing the coupling capacitance what technique we are using right now?
• Q: What’s the formula of the resistance?
• Expected Answer: Resistance = ρL/(width of metal)*(thickness of metal)
• Follow On Questions:
• Which material, we are using for Metal now a day?
• Before 0.18μm technology, which material we were using for Metal wire?
• Q: What’s the significance of calculating the cap value in the design
• Expected Ans: RC value of the wire/net is directly proportional to the delay of the wire/net. Delay has significance in the timing calculation. So RC value has significance in STA and SI.
• Follow on Questions:
• How are we using these cap and res values in the STA and SI?
• Which tool are you using for this

• Q: What do you mean by RC/ Extraction corners
• Q: What’s the Difference between Cworst and RC worst corner?
• Expected Ans: Cworst- Interconnect capacitance is worst , and in RC worst – product of Interconnect R and Interconnect C become worst (Not like both R & C worst- because that’s can’t possible).
• Follow On Questions:
• What are other corners?
• What’s the significance of RCworst / RCbest corner?
• How R and C plays their roles in deciding the sighoff corners.
• For signoff the design (closing the timing and all) how many parasitic corners are required?
Are these corners has any dependency on the technology and if yes, then how?
• Q: What are the process variations that contribute to RC corners in parasitic extraction?
• Expected answer:  Metal (copper) thickness, line width, dielectric thickness, etc. Process variation can be classified into two categories.  One is deterministic, the other is random. All the  manufacturing effects, such as wire width changes not corrected by Optical Proximity Correction (OPC), wire  thickness changes due to Chemical Mechanical Polishing (CMP), and effective resistance changes due to the cladding on copper interconnects and dishing of wide metal lines, can be accounted in extraction tools. etc
• Follow On Question:
• Why these are contributing?
• One by one interviewer can ask the details of the Process-variation parameters.
• If we will increase the widths of the metal – how it will effect on the cap and res value of metal?

In the next post, I will discuss few other questions related to face to face interview.

Timing based Interview Questions

Interview Questions

Usually there are 2 phase of interview- 

1. Over the phone (Phone Screen) and 
2. Face to Face.

Candidates have a wrong myth about the fact that interview over the phone is very easy and what interviewer can ask in that. When this year I have to recruit for my team then I has done a lot of phone screening and I have figured out that candidate usually take it very lightly. They don’t think the importance of the phone screening. 

Phone Screen Questions:

First we will discuss all those questions which can be the part of Phone screening. These can vary as per the Job profile and requirement but still more and less these are standard.

These are the questions which are not in much details but it will give the insight of your expertise and experience to the interviewer, which help him/them to further screening the profile.  

I will discuss the questions in several areas one by one.

Let’s start in the area of timing. Remember- I am also listing the Expected Ans in one word or one sentence. But expect the WHY/HOW as part of follow-on question. I have mentioned few follow-on questions also (without Ans). For the detailed ans of any topic, please read the different articles in the ( VLSI CONCEPTS ) http://vlsi-expert.com or refer any other book/weblink.
You Can also refer following book for more similar type of questions.
VLSI INTERVIEW QUESTION: Static Timing analysis : Puneet Mittal (Author)

Note:

Above Book is a Kindle edition. For that you have to download a "Free Kindle App" on you mobile/desktop/tablets. You can download Kindle App using following link.Amazon.com - Read eBooks using the FREE Kindle Reading App on Most Devices

Timing Related

• Q: In which tool you have experience related to timing/STA?  
• Expected answer (any): Synopsys Primetime, Magma Tekton, (etc  ...)
• Follow-On questions :
• Which one is industry standard?
• Which one is more accurate?
• On which version, you have worked?
• Any major difference in the 2 versions? (this question is going to ask if it’s the demand of job profile)
• How are you qualifying particular STA tool?
• Any 2 good STA tool with preferance. Also tell 1 good and 1 bad thing in both the tools.
• Q: In which part of the design we do the STA run.
• Expected answer: Any part we can do. But mostly once before the layout (after the synthesis) and then 2-3 times post layout. Signoff we usually do after the routing.
• Follow-On questions:
• On which side you have used?
• What’s the difference in terms of Input and accuracy in pre-layout and post-layout STA?
• Which one is more accurate and which one is fast?
• Why we want to do it twice or trice?
• Reference Article: Basic Of Timing Analysis ; First para of STA ; STA using EDA tool part2
• Q:  What are the input files required to run STA?
• Expected answer:  Gate level netlist, Parasitics file(SPEF/SBPF), Constraints (SDC or tcl), general setup scripts.
• Reference Article : STA using EDA tool part1
• Follow-On questions:
• What’s the source of these files? (means which one is coming from foundry/EDA vendor/internal)
• What’s the information present in these files which helps for delay calculation?
• What will happen in the absence of any/few of these files?
• In the absence of SPEF, which other data can be used?
• Expected answer: SDF, SBPF, DSPF, SPF. (But basically the intent of question is that if you don’t have any parasitic info in any available format, then SDF is the best solution).
• What if we don’t have the SDF also?
• Expected answer: Wire load model
• Which one is accurate and which one is fast to read in a STA tool out of SDF or SPEF?
• Expected answer: SDF is fast to read but SPEF is more accurate.
• Q: What is the main objective of timing closure in STA?
• Expected answer (any): Run necessary PVT/RC corners and close any negative slack path (hold slack/setup slack), Fixing any Timing DRC Error. Some time we have positive slack but because of constraint or say margin we have to set a margin value (like 5ps), so any path which has less then 5ps slack also has to fix. Same scenerio happen for negative case also. 

• Q:  What’s the different between Crosstalk and without crosstalk based STA analysis.
• Expected answer: In the cross talk based analysis, we want to see the impact of coupling capacitance and Noise on our circuit In addition to normal STA analysis. Without Crosstalk based analysis, we want to do normal delay analysis on the basis of skew/load/driving strength/clock pulse/frequency etc.
• Follow-On questions:
• Which files are necessary for crosstalk based STA run?
• Expected answer: Specially Interconnect parasitic file with coupling information.
• What will happen if we will not do the cross-talk based analysis?
• What should be the sequence of analysis?
• From which technology node onward, crosstalk based analysis become critical? And Why 
• Q: Why should crosstalk be avoided?
• Expected answer: Crosstalk causes signals to be delayed and can cause noise glitch on signals resulting in improper function.

• Q: Why are we using the timing constraints?
• Expected answer: The timing constraints define the operating environment the design/chip on which the final product should work such as clocks, clock frequency, margins. These constraint are defined in the .Libs files also and in the SDC also. 
• Follow-On questions:
• There are few constraints also present in the .lib files, then how SDC is different from that?
• Can I over write the constraint defined in the .lib files in my design?
• Pick any one constraint and explain the significance of that in the design.
• Reference Article : SDC
• Q: In the Hierarchical design, there are different Blocks. How are we capturing the timing information of those blocks in our design?
• Expected answer: Using the timing models of those blocks. Like ETM/QTM/ILM/dbs
• Follow-On questions:
• What’s the basic difference in the ETM and ILM models?
• What types of information are present in the ETM and ILM?
• Out of ETM and ILM, which one is more accurate?
• Which one you have used in your design?
• How are you generating that model?
• How accurate are those in terms of full-flat design?
• Reference Article : ETM Basics part1 ; Hierarchical Design part1 ; Hierarchical Design part2

• Q: What’s the main difference between OCV and AOCV.
• Expected Ans (or similar answer): On-Chip-Variation (OCV) timing analysis uses a constant derating factor; whereas AOCV applies derated value is a function of path-depth and possibly distance.

• Q: What’s the difference between PVT corner and RC corners?
• Expected Answer (or similar answer): PVT corners represent transistor Process (Slow /Fast) corner, and Voltage and Temperature operating conditions. RC corners are related to the metal (back-end) fabrication process. Width/thickness of wire can change by small amount during the fabrication. It will impact resistance and capacitance. So there are different interconnect RC corners.
• Follow-On Questions:
• How many PVT corners are there in 28nm/40nm technology node? Or (the node on which you are working/worked)
• What’s the difference between Slow and Fast corner?
• Why we need different corner for different temperature and voltage?
• Who is deciding these corners? (foundry/vendor/your company)

 In the next part, we will discuss More about the timing interview questions.

Recommended Book:
VLSI INTERVIEW QUESTION: Static Timing analysis : Puneet Mittal (Author)

Spice model Based Vlsi Interview Questions

I am listing few question asked by someone to me...

1. What do you means by Parasitic rule generation?
2. What are the different informations contain a spice model?
   
3. What are the different variation rules?
4. What is CMP effect? Why foundry define these rules?
   
5. What is IMD variation rules?Why foundry define these rules?
6. What is Trap rules?Why foundry define these rules?
7. What is Density variation rules in the RC rules? Why foundry define these rules?
8. Why there is need of RC rules?
9. Why we define resistance rules for metals and Vias?
10. if the thickness of metal increases , resistance increases or decreases?
    
11. What is etch rules?Why foundry define these rules?
12. What data is given in the spice model for generation of etch rules and how you calculate the etch value from that data?
13. What are thickness variation rules? how it effects the capacitance?
    
14. What is OPC rules?Why foundry define these rules?
15. What are the different types of Cap rules?
16. What do mean by best case, worst case, typical case?
17. What do you mean by 2D and 3D extraction of capacitance?
18. What is SPEF?
19. What is the role dielectric between two metal layers?
20. Why temperature coefficients are defined in the RC rules?
21. How we extract the capacitance from a real design?
22. What is the significance of floating metals and how it effects the capacitance?
23. What are the different constraint faced by the foundry during defining the rules?
24. if we consider an ideal case (means no CMP effect, no thickness variation , no width variation ), how it effects the rules?
    
25. Why now a days we use copper (Cu) and not Al for metal layers.

DRM Related VLSI interview questions

These are some Questions asked by some-one from me.

1. What are the difference between 45nm and 65nm routing rules? any new rule in the 45nm?
2. Why foundry define DRM, routing rules?
3. What is stack means? How many types of metal layers are in 65nm/45nm? Why metals are of different thickness?
4. Why thin metal are in lower position and thick metals are at upper position in a defined Stack?
   
5. What is the need of several types of metal layer in a design?
6. What do you mean by RDL layer? Why it requires?
   
7. How many types of routing? What is the sequence of that?
8. Power is routed first or clock is routed first ? and why?
9. what do you mean by notch rule? what is notch exactly (in terms of shape)?
10. Why we code routing rules?
11. What is stack VIA and why it requires?
12. Why foundry define min spacing rules/min width rules?
13. What do means by 65nm technology? Why it is saying 65nm?
14. In terms of foundry what are the main difference in 65nm and 45nm technology? (means why technology is changing continuously? explanations from the foundry point of view.)
15. What you think what are the challenges foundry face between two technology?
16. what do u mean by crosstalk?
17. How can you prevent this (crosstalk)?
18. what do u mean by grid and non grid routing? which one is preferable and why?
19. In magma tools , what is the concept behind sub grid?
20. What are the different types of Grids?
21. Why we use VIA array? Why not single large VIA in place of several via's?
22. What do you mean by VIA overhang? Why it is needed?
23. What do you mean by same grid spacing in VIAs?
24. What is shielding? How can U shield a clock rail?
25. The spacing between two single VIAs and spacing between via in VIA's array.. which one is smaller and why?
26. How many types of spacing rules?
27. How many types of width rules?
    
28. What is fat wire? Why rules are define separately for this?
29. How many layers are there in 130nm technology.
30. What is min area rules?
31. If the area of one metal layer is minimum from the min area rules then what should a designer do to prevent this?
32. Routing rules are dependent on the types of metal used. Is it true or false and why?
33. Why different types of metal layers (Al and Cu) are used in the design?
34. What are the different types of Pitch?
35. What do you mean by Pitch?
    

1. What is antenna rules? Why it define? Explain from the point of view of foundry also.
2. From where that accumulated charge come ?
3. How this charge effect a gate? and why?
   
4. How jumpers and diode prevent antenna violation?
5. Which type of diode is used to prevent antenna violation and how it works?
6. Where should be Jumper used?
7. What are the different types of antenna violation rules?

1. What is slotting rules?
2. Why it define?
3. How slots in the metal helps it?
4. What is density rules?

1. What is EM rules?
2. Why they are define?
3. How current density is dependent on temperature?
   
4. How many types of rule are there in EM section?
5. What is the significance of these rules from foundry point of view and from designer point of view?
6. What are the difference between average current density and RMS current density? OR How many types of current density and what are the difference between them?

1. Draw a diagram of CMOS. Explain different types of layers in it.
2. What do you mean by diffusion layers?
   
3. What is POD, NOD, Pwell, Nwell, N+,N++, P+, P++,Substrate, poly layer.
4. What is Oxidation, Lithography?
5. What is trench?
6. What is masking?
7. What is etching?