Spice model Based Vlsi Interview Questions

I am listing few question asked by someone to me...

1. What do you means by Parasitic rule generation?
2. What are the different informations contain a spice model?
   
3. What are the different variation rules?
4. What is CMP effect? Why foundry define these rules?
   
5. What is IMD variation rules?Why foundry define these rules?
6. What is Trap rules?Why foundry define these rules?
7. What is Density variation rules in the RC rules? Why foundry define these rules?
8. Why there is need of RC rules?
9. Why we define resistance rules for metals and Vias?
10. if the thickness of metal increases , resistance increases or decreases?
    
11. What is etch rules?Why foundry define these rules?
12. What data is given in the spice model for generation of etch rules and how you calculate the etch value from that data?
13. What are thickness variation rules? how it effects the capacitance?
    
14. What is OPC rules?Why foundry define these rules?
15. What are the different types of Cap rules?
16. What do mean by best case, worst case, typical case?
17. What do you mean by 2D and 3D extraction of capacitance?
18. What is SPEF?
19. What is the role dielectric between two metal layers?
20. Why temperature coefficients are defined in the RC rules?
21. How we extract the capacitance from a real design?
22. What is the significance of floating metals and how it effects the capacitance?
23. What are the different constraint faced by the foundry during defining the rules?
24. if we consider an ideal case (means no CMP effect, no thickness variation , no width variation ), how it effects the rules?
    
25. Why now a days we use copper (Cu) and not Al for metal layers.

DRM Related VLSI interview questions

These are some Questions asked by some-one from me.

1. What are the difference between 45nm and 65nm routing rules? any new rule in the 45nm?
2. Why foundry define DRM, routing rules?
3. What is stack means? How many types of metal layers are in 65nm/45nm? Why metals are of different thickness?
4. Why thin metal are in lower position and thick metals are at upper position in a defined Stack?
   
5. What is the need of several types of metal layer in a design?
6. What do you mean by RDL layer? Why it requires?
   
7. How many types of routing? What is the sequence of that?
8. Power is routed first or clock is routed first ? and why?
9. what do you mean by notch rule? what is notch exactly (in terms of shape)?
10. Why we code routing rules?
11. What is stack VIA and why it requires?
12. Why foundry define min spacing rules/min width rules?
13. What do means by 65nm technology? Why it is saying 65nm?
14. In terms of foundry what are the main difference in 65nm and 45nm technology? (means why technology is changing continuously? explanations from the foundry point of view.)
15. What you think what are the challenges foundry face between two technology?
16. what do u mean by crosstalk?
17. How can you prevent this (crosstalk)?
18. what do u mean by grid and non grid routing? which one is preferable and why?
19. In magma tools , what is the concept behind sub grid?
20. What are the different types of Grids?
21. Why we use VIA array? Why not single large VIA in place of several via's?
22. What do you mean by VIA overhang? Why it is needed?
23. What do you mean by same grid spacing in VIAs?
24. What is shielding? How can U shield a clock rail?
25. The spacing between two single VIAs and spacing between via in VIA's array.. which one is smaller and why?
26. How many types of spacing rules?
27. How many types of width rules?
    
28. What is fat wire? Why rules are define separately for this?
29. How many layers are there in 130nm technology.
30. What is min area rules?
31. If the area of one metal layer is minimum from the min area rules then what should a designer do to prevent this?
32. Routing rules are dependent on the types of metal used. Is it true or false and why?
33. Why different types of metal layers (Al and Cu) are used in the design?
34. What are the different types of Pitch?
35. What do you mean by Pitch?
    

1. What is antenna rules? Why it define? Explain from the point of view of foundry also.
2. From where that accumulated charge come ?
3. How this charge effect a gate? and why?
   
4. How jumpers and diode prevent antenna violation?
5. Which type of diode is used to prevent antenna violation and how it works?
6. Where should be Jumper used?
7. What are the different types of antenna violation rules?

1. What is slotting rules?
2. Why it define?
3. How slots in the metal helps it?
4. What is density rules?

1. What is EM rules?
2. Why they are define?
3. How current density is dependent on temperature?
   
4. How many types of rule are there in EM section?
5. What is the significance of these rules from foundry point of view and from designer point of view?
6. What are the difference between average current density and RMS current density? OR How many types of current density and what are the difference between them?

1. Draw a diagram of CMOS. Explain different types of layers in it.
2. What do you mean by diffusion layers?
   
3. What is POD, NOD, Pwell, Nwell, N+,N++, P+, P++,Substrate, poly layer.
4. What is Oxidation, Lithography?
5. What is trench?
6. What is masking?
7. What is etching?